Broadly defined, structured application-specific integrated circuits (ASICs) may attempt to reduce the effort, expense and risk of producing application-specific integrated circuits (ASIC) by standardizing portions of the physical implementation across multiple products. By amortizing the expensive mask layers of the device across a large set of different designs, the non-recurring engineering (NRE) seen by a particular customer for a customized ASIC can be significantly reduced. There may be additional benefits to the standardization of some portion of mask set, which may include improved yield through higher regularity and/or reduced manufacturing time from tape-out to packaged chip.
Compared to a field-programmable gate array (FPGA), the unit price of a structured ASIC solution may be reduced by an order of magnitude due to the removal of the storage and logic required for configuration storage and implementation. The unit cost of a structured ASIC may be somewhat higher than a full custom ASIC, primarily due to the imperfect fit between design requirements and a standardized base layer, with certain I/O, memory and logic capacities.
Structured ASIC products may be differentiated by the point at which the user customization occurs and how that customization is actually implemented. Most structured ASICs may only standardize transistors and the lowest levels of metal. A large set of metal and via masks may be needed in order to customize a product. This yields a marginal cost reduction for NRE. Manufacturing latency and yield benefits may also be compromised using this approach.
In some prior patents, all but one via layer in the mask set may be standardized. This single via layer may be implemented, for example, using one of at least two approaches:                A prototyping flow using direct-write e-beam technology may be used to eliminate the need for any mask layers.        A production flow may use a mask layer for the vias.        
The disadvantage of structured ASICs compared to FPGAs is that FPGAs do not require any user design information during manufacturing. Therefore, FPGA parts can be manufactured in larger volumes and can exist in larger inventories. This allows the latency of getting parts to customers in the right volumes to be reduced. FPGAs can also be modified after their initial configuration, which means that design bugs can be removed without requiring a fabrication cycle. Design improvements can be made in the field, and even done remotely, which removes the requirement of a technician to physically interact with the system.
An ideal ASIC device may combine the field programmability of FPGAs with the power and size efficiency of ASICs or structured ASICs.
Phase change memory materials may be used to store information reaching one of two physical phases: either an amorphous phase that may have high resistivity or a crystalline phase that may have low resistivity (while this is a typical way in which phase change memory materials work, the further possibility is envisioned of an atypical phase change memory material that may work in the opposite fashion or in some other fashion, and which may still be utilized in embodiments of the invention). One of the materials that may be used is chalcogenide. This material is often used, for example, in CD-RW and DVD-RW technology, where the phase change is performed by heating and cooling with a laser beam. It is also possible to change the state with an electric current. A high current may be used to create a higher temperature, and the material may then cool to the amorphous phase with a higher resistance. A medium current may be used to change the cooling to the crystalline phase with a lower resistance. A low current can be used to sense the resistance of the material without changing the phase of the material. This technology is patented and licensed by a company called Ovonyx.
There are other phase-change materials, such as oxide-based solid electrolytes. Memories using such technologies are sometimes referred to as Programmable Metallization Cells (PMCs).
A combination of resistive memory technology and via-configured structured ASICs can be used to offer an improved customizable integrated circuit, with low cost, area, and power of the structured ASIC, and the field programmability of an FPGA.